Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
Read operations usually are performed on floating gate memory cells using sense amplifiers. A sense amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 patent”), which is incorporated herein by reference for all purposes. The '158 patent discloses using a reference cell that draws a known amount of current. The '158 patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current mirror to mirror the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater.
Another sensing amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “'914 patent”), which is incorporated herein by reference for all purposes. The '914 patent discloses a sensing circuit for a multi-level floating gate memory cell or MLC, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11).
Also known in the prior art are symmetrical memory bank pairs, where a memory system comprises two (or other multiple of two) memory arrays of equal size. Only one of the two banks is read from or written to at any particular time. In the prior art, a separate reference cell circuit typically is used to compare to the memory cell that is read, and that comparison is used to determine the value of the memory cell. This prior art system can be adversely affected by changes in the parasitic capacitance of the system.
What is needed is a sensing circuit with an improved designs for using bit lines in an unused memory array to provide reference values in a more reliable manner than in the prior art.
Another challenge in the prior art is that memory systems can provide incorrect values if there is significant leakage current caused by defects in one or more transistors.
What is needed is a memory system that can perform a self-test operation to identify bit lines in a memory system with leakage currents that exceed an acceptable threshold.